Semiconductor device assemblies, including, but not limited to, memory chips, microprocessor chips, and imager chips, typically include a semiconductor device, such as a die, mounted on a package substrate. The package substrate and the die (or some portion of each) may be encased in a plastic protective covering (encapsulant) or metal heat spreader. The semiconductor device assembly may include various functional features, such as memory cells, processor circuits, and imager devices, and may include bond pads that are electrically connected to the functional features of the semiconductor device assembly. The semiconductor device assembly may include semiconductor devices stacked upon, and electrically connected to, one another by individual interconnects between adjacent devices within a package. The semiconductor device assemblies may include electrical interconnects (for example, solder balls) in an array pattern on the bottom of the package substrate to facilitate electrical connection to other semiconductor device assemblies or an electronic system.
Various methods and/or techniques may be employed to electrically interconnect adjacent semiconductor devices, semiconductor device packages, and/or substrates in a semiconductor device assembly. For example, in some applications two or more semiconductor device packages may be stacked one on top of another known as package-on-package (PoP) assembly. In particular, a PoP device may include an application processor in a lower package and one or more memory devices in an upper package mounted on the lower package. The memory devices may be electrically connected to the application processor using vias created in the lower package encapsulant that connect to interconnects (for example, solder balls) on the bottom of the upper package. The PoP device is configured to be mounted onto a main board or motherboard of an electronic system (such as, for example, a smart phone or tablet computer) using interconnects (for example, solder balls) on the bottom of the lower package. Accordingly, the application processor communicates directly with the memory devices in the PoP using electrically close connections (to minimize the negative electrical effects of longer electrical transmission lines) but is still able to connect directly to the main board of the electronic system to facilitate communications with other devices connected to the main board. One potential issue with PoP devices is the z height of the stacked semiconductor device packages. In some applications, the z height of a semiconductor device assembly may be limited due to space constraints. Additionally, in a PoP device, power and ground connections to each of the semiconductor device packages need to pass through each of the semiconductor device packages located below it in a PoP stack, which may cause a thermal issue and/or routing complexity within the semiconductor device assembly.
Another method of electrically connecting semiconductor device packages together is to place each semiconductor device package side-by-side, or adjacent to each other, on a substrate, such as a motherboard of an electronic system. The side-by-side configuration may require a larger footprint (i.e., x-y area) than the same devices in a PoP configuration, which may be problematic. For example, the area available on a substrate for semiconductor device packages may be limited depending on the application. Another potential disadvantage of a side-by-side configuration is that the semiconductor device packages cannot communicate directly between themselves. Rather, the communications must pass through the substrate or PCB, such as the motherboard, when communicating between two semiconductor device packages in a side-by-side configuration. In some instances, a system may include a large number of signals passing through the motherboard, and the motherboard may have many levels of electrical connections, thereby causing the electrical paths between the adjacent semiconductor device packages to be electrically far compared to the PoP device. This increased electrical length can potentially cause signal delays between the semiconductor device packages configured side-by-side on a motherboard. An increase in the signals through the motherboard may also cause thermal and/or routing issues.
As discussed above, a PoP package configuration provides close electrical connection between various semiconductor devices for applications where there is sufficient z height available to accommodate the stacked packages. However, due to the thermal, electrical, and/or physical drawbacks of the side-by-side configuration, a solution does not currently exist to provide close electrical connection between multiple semiconductor devices when z height is constrained, but there is x-y space available. Additional drawbacks and disadvantages may exist.
While the disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the disclosure is not intended to be limited to the particular forms disclosed. Rather, the intention is to cover all modifications, equivalents and alternatives falling within the scope of the disclosure as defined by the appended claims.